Oxide-Nitride-Oxide Stack Having Multiple Oxynitride Layers

ABSTRACT

A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stochiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application s a continuation of U.S. application Ser. No. 13/917,500, filed Jun. 13, 2013, which is a continuation of U.S. patent application Ser. No. 11/811,958, filed Jun. 13, 2007, which claims priority to U.S. Provisional Patent Application 60/931,947, filed May 25, 2007, all of which are incorporated by reference herein in their entirety.

TECHNICAL FIELD

This invention relates to semiconductor processing and, more particularly to an oxide-nitride-oxide stack having an improved oxide-nitride or oxynitride layer and methods of forming the same.

BACKGROUND OF THE INVENTION

Non-volatile semiconductor memories, such as a split gate flash memory, typically use a stacked floating gate type field effect transistors, in which electrons are induced into a floating gate of a memory cell to be programmed by biasing a control gate and grounding a body region of a substrate on which the memory cell is formed.

An oxide-nitride-oxide (ONO) stack is used as either a charge storing layer, as in silicon-oxide-nitride-oxide-silicon (SONOS) transistor, or as an isolation layer between the floating gate and control gate, as in a split gate flash memory.

FIG. 1 is a partial cross-sectional view of an intermediate structure for a semiconductor device 100 having a SONOS gate stack or structure 102 including a conventional ONO stack 104 formed over a surface 106 of a silicon substrate 108 according to a conventional method. In addition, the device 100 typically further includes one or more diffusion regions 110, such as source and drain regions, aligned to the gate stack and separated by a channel region 112. Briefly, the SONOS structure 102 includes a poly-silicon (poly) gate layer 114 formed upon and in contact with the ONO stack 104. The poly gate 114 is separated or electrically isolated from the substrate 108 by the ONO stack 104. The ONO stack 104 generally includes a lower oxide layer 116, a nitride or oxynitride layer 118 which serves as a charge storing or memory layer for the device 100, and a top, high-temperature oxide (HTO) layer 120 overlying the nitride or oxynitride layer.

One problem with conventional SONOS structures 102 and methods of forming the same is the poor data retention of the nitride or oxynitride layer 118 that limits the device 100 lifetime and/or its use in several applications due to leakage current through the layer.

Another problem with conventional SONOS structures 102 and methods of forming the same is the stochiometry of the oxynitride layer 118 is neither uniform nor optimized across the thickness of the layer. In particular, the oxynitride layer 118 is conventionally formed or deposited in a single step using a single process gas mixture and fixed or constant processing conditions in an attempt to provide a homogeneous layer having a high nitrogen and high oxygen concentration across the thickness of the relatively thick layer. However, due to top and bottom effects this results in nitrogen, oxygen and silicon concentrations, which can vary throughout the conventional oxynitride layer 118. The top effect is caused by the order in which process gases are shut off following deposition. In particular, the silicon containing process gas, such as silane, is typically shut off first resulting in a top portion of the oxynitride layer 118 that is high in oxygen and/or nitride and low in silicon. Similarly, the bottom effect is caused by the order in which process gases are introduced to initiate deposition. In particular, the deposition of the oxynitride layer 118 typically follows an annealing step, resulting in a peak or relatively high concentration (NH₃) at the beginning of the deposition process and producing in a bottom portion of the oxynitride layer that is low in oxygen and silicon and high in nitrogen. The bottom effect is also due to surface nucleation phenomena in which that oxygen and silicon that is available in the initial process gas mixture preferentially reacts with silicon at the surface of the substrate and does not contribute to the formation of the oxynitride layer. Consequently, the charge storage characteristics, and in particular programming and erase speed and data retention of a memory device 100 made with the ONO stack 104, are adversely effected.

Accordingly, there is a need for a memory device having an ONO stack with an oxynitride layer as a memory layer that exhibits improved programming and erase speed and data retention. There is a further need for a method or process of forming an ONO stack having an oxynitride layer that exhibits improved oxynitride stochiometry.

The present invention provides a solution to these and other problems, and offers further advantages over conventional ONO stacks or memory layers and methods of forming the same.

BRIEF DESCRIPTION OF THE DRAWINGS

These and various other features and advantages of the present invention will be apparent upon reading of the following detailed description in conjunction with the accompanying drawings and the appended claims provided below, where:

FIG. 1 (prior art) is a block diagram illustrating a cross-sectional side view of an intermediate structure for a memory device for which a method having an oxide-nitride-oxide (ONO) stack formed according to conventional method;

FIG. 2 is a block diagram illustrating a cross-sectional side view of a portion of a semiconductor device having an ONO structure including a multi-layer charge storing layer according to an embodiment of the present invention;

FIG. 3 is flow chart of a method for forming an ONO structure including a multi-layer charge storing layer according to an embodiment of the present invention; and

FIG. 4 is a graph showing an improvement in data retention for a memory device using a memory layer formed according to the present invention as compared to a memory device using a conventional memory layer.

DETAILED DESCRIPTION

The present invention is directed generally to an oxide-nitride-oxide (ONO) structure including a multi-layer charge storing layer and methods for making the same. The ONO structure and method are particularly useful for forming a memory layer in a memory device, such as a silicon-oxide-nitride-oxide-silicon (SONOS) memory transistor.

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures, and techniques are not shown in detail or are shown in block diagram form in order to avoid unnecessarily obscuring an understanding of this description.

Reference in the description to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification do not necessarily all refer to the same embodiment. The term “to couple” as used herein may include both to directly connect and to indirectly connect through one or more intervening components.

Briefly, the method involves forming a multi-layer charge storing layer including multiple oxynitride layers, such as silicon oxynitride (Si₂N₂O) layers, having differing concentrations of Oxygen, Nitrogen and/or Silicon. Generally, the oxynitride layers are formed at higher temperatures than nitride or oxynitride layers in conventional ONO structures, and each of the layers are formed using differing process gases mixtures and/or at differing flow rates. Preferably, the oxynitride layers include at least a top oxynitride layer and a bottom oxynitride layer. More preferably, the stochiometric compositions of the layers is tailored or selected such that the lower or bottom oxynitride has a high oxygen and silicon content, and the top oxynitride layer has high silicon and a high nitrogen concentration with a low oxygen concentration to produce a silicon-rich nitride or oxynitride. The silicon-rich and oxygen-rich bottom oxynitride layer reduces stored charge loss without compromising device speed or an initial (beginning of life) difference between program and erase voltages. The silicon-rich, oxygen-lean top oxynitride layer increases a difference between programming and erase voltages of memory devices, thereby improving device speed, increasing data retention, and extending the operating life of the device.

Optionally, the ratio of thicknesses between the top oxynitride layer and the bottom oxynitride layer can be selected to facilitate forming of the oxynitride layers over a first oxide layer of an ONO structure following the step of forming the first oxide layer using a steam anneal.

An ONO structure and methods for fabricating the same according to various embodiments of the present invention will now be described in greater detail with reference to FIGS. 2 through 4.

FIG. 2 is a block diagram illustrating across-sectional side view of a portion of a semiconductor memory device 200 having an ONO structure including a multi-layer charge storing layer according to one embodiment of the present invention. Referring to FIG. 2, the memory device 200 includes a SONOS gate stack 202 including an ONO structure 204 formed over a surface 206 of silicon layer on a substrate or a silicon substrate 208. In addition, the device 200 further includes one or more diffusion regions 210, such as source and drain regions, aligned to the gate stack 202 and separated by a channel region 212. Generally, the SON structure 202 includes a poly-silicon or poly gate layer 214 formed upon and in contact with the ONO structure 204 and a portion of the silicon layer or substrate 208. The poly gate 214 is separated or electrically isolated from the substrate 208 by the ONO structure 204. The ONO structure 204 includes a thin, lower oxide layer or tunneling oxide layer 216 that separates or electrically isolates the gate stack 202 from the channel region 212, a top or blocking oxide layer 218, and a multi-layer charge storing layer including multiple nitride containing layers. Preferably, as noted above and as shown in FIG. 2, the multi-layer charge storing layer includes at least two oxynitride layers, including a top oxynitride layer 220A and a bottom oxynitride layer 220B.

Generally, the substrate 208 may include any known silicon-based semiconductor material including silicon, silicon-germanium, silicon-on-insulator, or silicon-on-sapphire substrate. Alternatively, the substrate 208 may include a silicon layer formed on a non-silicon-based semiconductor material, such as gallium-arsenide, germanium, gallium-nitride, or aluminum-phosphide. Preferably, the substrate 208 is a doped or undoped silicon substrate.

The lower oxide layer or tunneling oxide layer 216 of the ONO structure 204 generally includes a relatively thin layer of silicon dioxide (SiO₂) of from about 15 angstrom (Å) to about 22 Å, and more preferably about 18 Å. The tunneling oxide layer 216 can be formed or deposited by any suitable means including, for example, being thermally grown or deposited using chemical vapor deposition (CVD). In a preferred embodiment, the tunnel oxide layer is formed or grown using a steam anneal. Generally, the process involves a wet-oxidizing method in which the substrate 208 is placed in a in a deposition or processing chamber, heated to a temperature from about 700° C. to about 850° C., and exposed to a wet vapor for a predetermined period of time selected based on a desired thickness of the finished tunneling oxide layer 216. Exemplary process times are from about 5 to about 20 minutes. The oxidation can be performed at atmospheric or at low pressure.

As noted above, the multi-layer charge storing layer generally includes at least two oxynitride layers having differing compositions of silicon, oxygen and nitrogen, and can have an overall thickness of from about 70 Å to about 150 Å, and more preferably about 100 Å. In a preferred embodiment the oxynitride layers are formed or deposited in a low pressure CVD process using a silicon source, such as slime (SiH₄), chlorosilane (SiH₃Cl), dichlorosilane (SiH₂Cl₂), tetrachlorosilane (SiCl₄) or BisTertiaryButylAmino Silane (BTBAS), a nitrogen source, such as nitrogen ammonia (NH₃), nitrogen trioxide (NO₃) or nitrous oxide (N₂O), and an oxygen-containing gas, such as oxygen (O₂) or N₂O. Alternatively, gases in which hydrogen has been replaced by deuterium can be used, including, for example, the substitution of deuterated-ammonia (ND₃) for NH₃. The substitution of deuterium for hydrogen advantageously passivates Si dangling bonds at the silicon-oxide interface, thereby increasing an NBTI (Negative Bias Temperature Instability) lifetime of the devices.

For example, the lower or bottom oxynitride layer 220B can be deposited over the tunneling oxide layer 216 by placing the substrate 208 in a deposition chamber and introducing a process gas including N₂O, NH₃ and DCS, while maintaining the chamber at a pressure of from about 5 millitorr (mT) to about 500 mT, and maintaining the substrate at a temperature of from about 700° C. to about 850° C. and more preferably at least about 780° C., for a period of from about 2.5 minutes to about 20 minutes. In particular, the process gas can include a first gas mixture of N₂O and NH₃ mixed in a ratio of from about 8:1 to about 1:8 and a second gas mixture of DCS and NH₃ mixed in a ratio of from about 1:7 to about 7:1, and can be introduced at a flow rate of from about 5 to about 200 standard cubic centimeters per minute (sccm). It has been found that an oxynitride layer produced or deposited under these condition yields a silicon-rich, oxygen-rich, bottom oxynitride layer 220B, that decrease the charge loss rate after programming and after erase, which is manifested in a small voltage shift in the retention mode.

The top oxynitride layer 220A can be deposited over the bottom oxynitride layer 220B in a CVD process using a process gas including N₂O, NH₃ and DCS, at a chamber pressure of from about 5 mT to about 500 mT, and at a substrate temperature of from about 700° C. to about 850° C. and more preferably at least about 780° C., for a period of from about 2.5 minutes to about 20 minutes, In particular, the process gas can include a first gas mixture of N₂O and NH₃ mixed in a ratio of from about 8:1 to about 1:8 and a second gas mixture of DCS and NH₃ mixed in a ratio of from about 1:7 to about 7:1, and can be introduced at a flow rate of from about 5 to about 20 sccm. It has been found that an oxynitride layer produced or deposited under these condition yields a silicon-rich, nitrogen-rich, and oxygen-lean top oxynitride layer 220A, which it proves the speed and increases of the initial difference between program and erase voltage without compromising a charge loss rate of memory devices made using an embodiment of the inventive ONO structure 204, thereby extending the operating life of the device.

Preferably, the top oxynitride layer 220A is deposited sequentially in the same tool used to form the bottom oxynitride layer 220B, substantially without breaking vacuum on the deposition chamber. More preferably, the top oxynitride layer 220A is deposited substantially without altering the temperature to which the substrate 208 was heated during deposition of the bottom oxynitride layer 220B. In one embodiment, the top oxynitride layer 220A is deposited sequentially and immediately following the deposition of the bottom oxynitride layer 220B by decreasing the flow rate of the N₂O/NH₃ gas mixture relative to the DCS/NH₃ gas mixture to provide the desired ratio of the gas mixtures to yield the silicon-rich, nitrogen-rich, and oxygen-lean top oxynitride layer 220A.

In certain embodiments, another oxide or oxide layer (not shown in these figures) is formed after the formation of the ONO structure 204 in a different area on the substrate or in the device using a steam oxidation. In this embodiment, the top oxynitride layer 220A and top oxide layer 218 of the ONO structure 204 are beneficially steam annealed during the steam oxidation process. In particular, steam annealing improves the quality of the top oxide layer 218 reducing the number of traps formed near a top surface of the top oxide layer and near a top surface of the underlying top oxynitride layer 220A, thereby reducing or substantially eliminating an electric field that could otherwise form across the top oxide layer, which could result in back streaming of charge carriers therethrough and adversely affecting data or charge retention in the charge storing layer.

A suitable thickness for the bottom oxynitride layer 220B has been found to be from about 10 Å to about 80 Å, and a ratio of thicknesses between the bottom layer and the top oxynitride layer has been found to be from about 1:6 to about 6:1, and more preferably at least about 1:4.

The top oxide layer 218 of the ONO structure 204 includes a relatively thick layer of SiO₂ of from about 30 Å to about 70 Å, and more preferably about 45 Å. The top oxide layer 218 can be formed or deposited by any suitable means including, for example, being thermally grown or deposited using CVD. In a preferred embodiment, the top oxide layer 218 is a high-temperature-oxide (HTO) deposited using CVD process. Generally, the deposition process involves exposing the substrate 208 to a silicon source, such as silane, chlorosilane, or dichlorosilane, and an oxygen-containing gas, such as O₂ or N₂O in a deposition chamber at a pressure of from about 50 mT to about 1000 mT, for a period of from about 10 minutes to about 120 minutes while maintaining the substrate at a temperature of from about 650° C. to about 850° C.

Preferably, the top oxide layer 218 is deposited sequentially in the same tool used to form the oxynitride layers 220A, 220B. More preferably, the oxynitride layers 220A, 220B, and the top oxide layer 218 are formed or deposited in the same tool used to grow the tunneling oxide layer 216. Suitable tools include, for example, an ONO AVP, commercially available from AVIZA technology of Scotts Valley, Calif.

A method or forming or fabricating an ONO stack according to one embodiment of the present invention will now be described with reference to the flowchart of FIG. 3.

Referring to FIG. 3, the method begins with forming a first oxide layer, such as a tunneling oxide layer, of the ONO structure over a silicon containing layer on a surface of a substrate (step 300). Next, the first layer of a multi-layer charge storing layer including nitride is formed on a surface of the first oxide layer (step 302). As noted above, this first layer or bottom oxynitride layer can be formed or deposited by a CVD process using a process gas including N₂O/NH₃ and DCS/NH₃ gas mixtures in ratios and at flow rates tailored to provide a silicon-rich and oxygen-rich oxynitride layer. The second layer of the multi-layer charge storing layer is then formed on a surface of the first layer (step 304). The second layer has a stochiometric composition of oxygen, nitrogen and/or silicon different from that of the first layer. In particular, and as noted above, the second or top oxynitride layer can be formed or deposited by a CVD process using a process gas including DCS/NH₃ and N₂O/NH₃ gas mixtures in ratios and at flow rates tailored to provide a silicon-rich, oxygen-lean top oxynitride layer. Finally, a second oxide layer of the ONO structure is formed on a surface of the second layer of the multi-layer charge storing layer (step 306). As noted above, this top or blocking oxide layer can be formed or deposited by any suitable means, but is preferably deposited in a CVD process. In one embodiment the top or second oxide layer is a high temperature oxide deposited in a HTO CVD process. Alternatively, the top or blocking oxide layer can be thermally grown, however it will be appreciated that in this embodiment the oxynitride thickness must be adjusted or increased as some of the top oxynitride will be effectively consumed or oxidized during the process of thermally growing the blocking oxide layer.

Optionally, the method may further include the step of forming or depositing a silicon containing layer on a surface of the second oxide layer to form a SONOS stack or structure (step 308). The silicon containing layer can be, for example, a polysilicon layer deposited by a CVD process to form a control gate of a SONOS transistor or device.

A comparison of data retention for a memory device using a memory layer formed according to an embodiment of the present invention as compared to a memory device using a conventional memory layer will now be made with reference to FIG. 4. In particular, FIG. 4 illustrates the change in threshold voltage of devices in an electronically erasable programmable read-only memory (EEPROM) during programming (VTP) during erase (VTE) over device life for an EEPROM made using a conventional ONO structure and an ONO structure having a multi-layer oxynitride layer. In gathering data for this figure both devices were pre-cycled for 100K cycles at an ambient temperature of 85° C.

Referring to FIG. 4, the graph or line 402 illustrates the change over time of a VIP for an EEPROM made using a conventional ONO structure having a single oxynitride layer without refreshing the memory after the initial writing—program or erase. Actual data points on line 402 are shown by unfilled circles, the remainder of the line showing an extrapolation of VTP to a specified end-of-life (EOL) for the EEPROM. Graph or line 404 illustrates the change over time of a VTE for the EEPROM made using a conventional ONO structure. Actual data points on line 404 are shown by filled circles, and the remainder of the line shows an extrapolation of VTE to EOL for the EEPROM. Generally, the specified difference between the VTE and VTP for an EEPROM at EOL is at least 0.5 V to be able to identify or sense the difference between the program and erase state. As seen from this figure an EEPROM made using a conventional ONO structure has a difference between VTE and VTP of about 0.35V at a specified EOL of 20 years. Thus, an EEPROM made using a conventional ONO structure and operated under the conditions described above will fail to meet the specified operating life by at least about 17 years.

In contrast, the change in VTP and VTE over time for an EEPROM made using an ONO structure having a multi-layer oxynitride layer, illustrated by lines 406 and 408 respectively, shows a difference between VTE and VTP of at least about 1.96V at the specified EOL. Thus, an EEPROM made using an ONO structure according to an embodiment of the present invention will meet and exceed the specified operating life of 20 years. In particular, graph or line 406 illustrates the change over time VTP for an EEPROM using an ONO structure according to an embodiment of the present invention. Actual data points on line 406 are shown by unfilled squares, the remainder of the line showing an extrapolation of VTP to the specified EOL. Graph or line 408 illustrates the change over time of VTE for the EEPROM, and actual data points on line 408 are shown by filled squares, the remainder of the line showing an extrapolation of VTE to EOL.

Although shown and described above as having only two oxynitride layer, i.e., a top and a bottom layer, the present invention is not so limited, and the multi-layer charge storing layer can include any number, n, of oxynitride layers, any or all of which may have differing stochiometric compositions of oxygen, nitrogen and/or silicon. In particular, multi-layer charge storing layers having up to five oxynitride layers each with differing stochiometric compositions have been produced and tested. However, as will be appreciated by those skilled in the art it is generally desirable to utilize as few layers as possible to accomplish a desired result, reducing the process steps necessary to produce the device, and thereby providing a much simpler and more robust manufacturing process. Moreover, utilizing as few layers as possible also results in higher yields as it is simpler to control the stoichiometric composition and dimensions of the fewer layers.

It will further be appreciated that although shown and described as part of a SONOS stack in a SONOS memory device, the ONO structure and method of the present invention is not so limited, and the ONO structure can be used in or with any semiconductor technology or in any device requiring a charge storing or dielectric layer or stack including, for example, in a split gate flash memory, a TaNOS stack, in a 1T (transistor) SONOS cell, a 2T SONOS cell, a 3T SONOS cell, a localized 2-bit cell, and in a multilevel programming or cell, without departing from the scope of the invention.

The advantages of ONO structures and methods of forming the same according to an embodiment of the present invention over previous or conventional approaches include:(i) the ability to enhance data retention in memory devices using the structure by dividing the oxynitride layer into a plurality of films or layers and tailoring the oxygen, nitrogen and silicon profile across each layer; (ii) the ability to enhance speed of a memory device without compromising data retention; (iii) the ability to meet or exceed data retention and speed specifications for memory devices using an ONO structure of an embodiment of the present invention at a temperature of at least about 125° C.; and (iv) provide heavy duty program erase cycles of 100,000 cycles or more.

The foregoing description of specific embodiments and examples of the invention have been presented for the purpose of illustration and description, and although the invention has been described and illustrated by certain of the preceding examples, it is not to be construed as being limited thereby. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and many modifications, improvements and variations within the scope of the invention are possible in light of the above teaching. It is intended that the scope of the invention encompass the generic area as herein disclosed, and by the claims appended hereto and their equivalents. The scope of the present invention is defined by the claims, which includes known equivalents and unforeseeable equivalents at the time of filing of this application. 

1-20. (canceled)
 21. A method of forming a semiconductor device, the method comprising: forming a tunneling oxide layer; forming a first layer of a multi-layer charge storing layer over the tunneling oxide layer, wherein the first layer comprises at least silicon and oxygen; forming a second layer of the multi-layer charge storing layer over the first layer, wherein the second layer comprises at least silicon and nitrogen, wherein a stoichiometric composition of the first layer is different from a stoichiometric composition of the second layer; and forming a blocking oxide layer over the second layer of the multi-layer charge storing layer.
 22. The method of claim 21, further comprising steam annealing at least the second layer of the multi-layer charge layer.
 23. The method of claim 22, wherein the steam annealing reduces a number of traps formed near a top surface of the second layer of the multi-layer charge.
 24. The method of claim 22, wherein the steam annealing is performed after forming the blocking oxide layer.
 25. The method of claim 24, wherein steam annealing reduces a number of traps formed near a top surface of the blocking oxide layer.
 26. The method of claim 21, wherein the first layer and the second layer of the multi-layer charge storing layer are formed sequentially without breaking vacuum in a deposition chamber.
 27. The method of claim 26, wherein the first layer and the second layer of the multi-layer charge storing layer are formed at a same substrate temperature.
 28. The method of claim 26, wherein each of the first layer and the second layer of the multi-layer charge storing layer is formed at between 700° C. and 850° C.
 29. The method of claim 26, wherein forming the second layer comprises decrease a flow rate ratio of a nitrous oxide (N₂O)/ammonia (NH₃) gas mixture relative to dichlorosilane (SiH₂Cl₂)/ammonia (NH₃) gas mixture.
 30. The method of claim 21, wherein at least one of the first layer and the second layer of the multi-layer charge storing layer is formed using deuterated-ammonia (ND₃).
 31. The method of claim 21, wherein the first layer of the multi-layer charge storing layer includes a thickness of between 10 Angstroms and 80 Angstroms.
 32. The method of claim 21, wherein a thickness ratio of the first layer relative to the second layer of the multi-layer charge storing layer is at least 1:4.
 33. The method of claim 21, wherein a concentration of oxygen is greater in the first layer than in the second layer.
 34. The method of claim 21, wherein each of the first layer and the second layer of the multi-layer charge storing layer comprises silicon, nitrogen, and oxygen.
 35. The method of claim 21, wherein the second layer of the multi-layer charge storing layer comprises a silicon-rich nitride.
 36. The method of claim 21, wherein the semiconductor device is a semiconductor memory device.
 37. The method of claim 21, wherein the tunneling oxide layer comprises silicon dioxide (SiO₂).
 38. The method of claim 21, wherein the tunneling oxide layer includes a thickness of between 15 Angstroms and 22 Angstroms.
 39. The method of claim 21, wherein forming the tunneling oxide layer comprises steam annealing.
 40. The method of claim 21, wherein the blocking oxide layer includes a thickness of between 10 Angstroms and 80 Angstroms. 